The present invention relates to integrated circuits and, more particularly, to a method of forming an alignment feature in or on a multi-layered semiconductor structure for aligning a lithography mask and that may be used in connection with an Electron Projection Lithography (EPL) tool and process (also known in the art by the tradename SCALPEL).
Optical lithography tools use a single light source (e.g., a laser) to align and expose a lithography mask on a semiconductor wafer. In a typical semiconductor wafer process that uses photolithography, alignment marks do not generate a high backscattered electron contrast when probed with the electron beam in an electron beam lithography exposure tool. Therefore, detection of typical photolithography alignment marks using an electron beam with EPL (or SCALPEL (Scattering with Angular Limitation In Projection Electron-Beam Lithography)) is not possible. Only after alignment marks are defined on or in the wafer, that can be detected with electrons, can an EPL tool be used to expose the mask features on the wafer. Thus the EPL tool uses an electron beam source to align the lithography mask, and an electron beam source to expose the mask on the wafer.
There, thus, exists a need in the art for a method and structure that permits the use of an electron-beam source for both alignment and exposure of a lithography mask on a semiconductor wafer.
The present invention is directed to a method of forming an alignment feature in or on a multi-layered semiconductor structure for aligning a lithography mask and that may be used in connection with an Electron Projection Lithography (EPL) tool and process. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
A SCALPEL tool uses alignment features for, inter alia, lithography mask alignment and registration. Residual errors introduced during fabrication of a multi-layered semiconductor structure may be minimized by using the same electron optical configuration (i.e., electron optical energy source) for alignment of a lithography mask and for exposure of the mask features on the semiconductor structure, i.e., in an electron beam sensitive resist on the structure, for example.
Alignment features or marks are fabricated on a semiconductor structure (i.e., wafer) for aligning a lithography mask to the structure; the lithography mask defining a plurality of features to be exposed and etched in the semiconductor structure. In accordance with the present invention, a 100 kV electron beam source may be used by a SCALPEL tool for both the alignment of a lithography mask and exposure of the features defined by the mask. Forming an alignment feature in the semiconductor structure of a relatively high atomic number material provides a material that will back-scatter electrons which may be detected by the SCALPEL tool to determine the location of the alignment feature. Moreover, the present invention further provides for use of a single energy source in a SCALPEL tool where the alignment feature is formed of silicon dioxide and defined in a layer of the semiconductor structure. In that case, the detection sensitivity of the SCALPEL tool must be greater than for high atomic number materials or the mark topography must contribute sufficient backscattered electron contrast so that the subtle differences in the amount of the electrons reflected by the silicon dioxide alignment feature and by other semiconductor layers may be detected.
The present invention also generally applies to a method of aligning a lithography mask on a semiconductor structure using an alignment feature formed in or on the structure and of a material that back-scatters a greater amount of electrons than any of the other materials from which the semiconductor structure is constructed. An electron beam is directed at the structure and the electrons back-scattered by the alignment feature may be detected to determine the location of the alignment feature. A lithography mask may then be aligned for exposure using the alignment feature previously detected.
The present invention is directed to a method of forming a multi-layered semiconductor structure having a silicon substrate, and comprises forming an alignment feature of a material that is not silicon in the silicon substrate and aligning a lithography mask using the alignment feature and using a SCALPEL tool having an electron beam source for directing an electron beam toward the silicon substrate. The alignment feature back-scatters a greater amount of electrons toward the electron beam source than the silicon substrate.
The present invention is also directed to a method of forming a multi-layered semiconductor structure consisting of layers of silicon, silicon dioxide, and polysilicon, and comprises forming an alignment feature on the polysilicon layer of the semiconductor structure, and aligning a lithography mask using the alignment feature and using a SCALPEL tool having an electron beam source for directing an electron beam toward the polysilicon layer. The alignment feature back-scatters a greater amount of electrons toward the electron beam source (toward an electron beam sensitive detector) than the polysilicon layer.
The present invention is further directed to a method of forming a multi-layered semiconductor structure consisting of layers of silicon and silicon dioxide, and comprises forming an alignment feature in the silicon dioxide, and aligning a lithography mask using the alignment feature and using a SCALPEL tool having an electron beam source for directing an electron beam toward the silicon substrate. The alignment feature back-scatters a greater amount of electrons toward the electron beam source than the polysilicon layer.
The present invention is also directed to a semiconductor structure constructed in accordance with the various method embodiments of the present invention.
Other objects and features of the present invention will become apparent from the following detailed description, considered in conjunction with the accompanying drawing figures. It is to be understood, however, that the drawings, which are not to scale, are designed solely for the purpose of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.